Journal of Computers, Vol 6, No 9 (2011), 1971-1975, Sep 2011
doi:10.4304/jcp.6.9.1971-1975

A Modified Technique for Analysis of Synchronous Counters Constructed with Flip-flops

Dangui Yan, Ruijun Tong, Chengchang Zhang, Changyong Li

Abstract


Some methods of fabrication make it economically attractive to construct counters (and other devices) by connecting sets of identical flip-flops(FFs), if the FFs have a common clock input, the state transitions of the whole counters are as rapid as the state transitions of each FFs, so that the counter is further restricted to be synchronous. In order to simplify the process for analysis of synchronous counters constructed with flip-flops, a simple and successful method is proposed. Using this method, the state transition equations obtained from logic diagram of counter are converted to standard sum-of-products forms(SOPs). By finding out the logic principle for achieving the value of logic function based on the standard SOPs, the values of next state can be directly obtained without any Boolean calculation. Analysis for a 3-bits counter shows that this method eliminates complex calculations， and makes the process of obtaining next state value and developing truth table more rapid and convenient.


Keywords


counter, synchronous, flip-flops, equation, calculation, sum-of-products forms

References


[1] Stan, M.R.; Tenca, A.F.; Ercegovac, M.D. Long and fast up/down counters. IEEE Trans on computers, Vol. 47, No. 7, July 1998, pp. 722-735.
http://dx.doi.org/10.1109/12.709372

[2] ZENG Xiao-pang; WANG Peng-jun. Design of four valued synchronous reversible counter based on the theory of three essential circuit elements. Journal of Zhejiang University(Science Edition), 2009, vol.36(5), pp. 553-556.

[3] YE Xi-en, TAO Wei-jiong, WANG Lun-yao. A low power terminary D type flip-flop design based on clock gating technique . Journal of Circuits and Systems, 2006, 11(3), pp. 106-109.

[4] Vaquero, A.R.; Aguilo, J. Gateless synchronous counters with D flip-flops. Electronics Letters Vol.14 (16), 1978, pp. 496-498.
http://dx.doi.org/10.1049/el:19780333

[5] F. B. Manning. Autonomous, Synchronous Counters Constructed Only of J-K Flip-Flops. S.M. thesis, available in microfiche from MIT Barker Engineering Library or in paperback as Project MAC, Massachusetts Inst. Technol.,Cambridge, MA, Tech. Rep. Period Counlter Comment TR-96, 1972.

[6] YE Xi-en, TAO Wei-jiong, WANG Lun-yao. A low power ter nary D type flip-flop design based on clock gating technique. Journal of Circuits and Systems, 2006, 11(3), pp.106-109.

[7] WU Zhong guang 1; YANG Yu zhi. The Method of Real Time and Synchronous Counting for High Speed Multi-Event by CPLD. Journal of Sichuan University (Natural Science Edition). 2002,vol.39(1), pp. 62-64.

[8] WU Zhong guang; YANG Yu zhi. The Method of Real Time and Synchronous Counting for High Speed Multi-Event by CPLD. Journal of Sichuan University (Natural Science Edition). 2002,vol.39(1), pp. 62-64.

[9] Misra, S.K.; Kolagotia, R.K.; Srinivas, H.R.; Mo, J.C.; Diamondstein, M.S. VLSI implementation of a 300-MHz 0.35-μm CMOS 32-bit auto-reloadable binary synchronous counter with optimal test overhead delay . VLSI Design, 1998. Proceedings. Eleventh International Conference on, 1998, pp. 326-329.

[10] Aguirre-Hernandez, M.; Linares-Aranda, M. A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems. Devices, Circuits and Systems, Proceedings of the 6th International Caribbean Conference on, 2006, pp. 293-297.

[11] Misra, S.K.; Kolagotia, R.K.; Srinivas, H.R.; Mo, J.C.; Diamondstein, M.S. VLSI implementation of a 300-MHz 0.35-μm CMOS 32-bit auto-reloadable binary synchronous counter with optimal test overhead delay . VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on, pp. 326-329.

[12] Aguirre-Hernandez, M.; Linares-Aranda, M. A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems. Devices, Circuits and Systems, Proceedings of the 6th International Caribbean Conference on, 2006, pp. 293-297.

[13] Thomas L.Floyd. Digital Fundamentals. 9th ed. P. cm.2004, pp. 398-403.

[14] Wang Yuyin. Digital circuit and logic design. 3rd ed. Higher education press, 2008, pp.181.

[15] WANG Shi-yuan, XIE Kai-ming, SHI Ya-wei, CHEN Meng-gang, LONG Zheng-ji. Implementation of a New FPGA-Based Controllable Frequency Divider. Journal of Southwest University (Natural Science Edition). 2007, vol. 29(1), pp. 89-93.

[16] Frank B.Manning AND Rober R. Fenichel. Synchronous Counters Constructed Entirely of J-K Flip-Flops. IEEE Trans on computers, March 1976, pp. 300-306.

[17] Manning, Frank B.; Fenichel, Robert R. Synchronous Counters Constructed Entirely of J-K Flip-Flops . IEEE Transactions on Computers, Vol: C-25 (3), 1976, pp. 300-306.
http://dx.doi.org/10.1109/TC.1976.5009257

[18] L. Wang and A.E.A. Almani. Fast conversion algorithm for very large Boolean functions. Electronics letters, Vol. 36, No. 16, August 2000, pp. 1370-1371.
http://dx.doi.org/10.1049/el:20001009

[19] Michel E. Holder. A Modified Karnaugh Map Technique. IEEE Trans on education, Vol. 48, NO. 1, February 2005. pp. 206-207.
http://dx.doi.org/10.1109/TE.2004.832879

[20] Dean, K.J. An extension of the use of karnaugh maps in the minimization of logical functions. Radio and Electronic Engineer. Vol.35(5), 1968, pp.294-296.
http://dx.doi.org/10.1049/ree.1968.0042


Full Text: PDF


Journal of Computers (JCP, ISSN 1796-203X)

Copyright @ 2006-2013 by ACADEMY PUBLISHER – All rights reserved.