Easing Instruction Queue Competition among Threads in RMT

Abstract

[1] Daniel Sorin, Fault Tolerant Computing Architecture[M]. Morgan&Claypool publishers. 2009.

[2] T. C. May and M. H. Woods, "Alpha-Particle-Induced Soft Errors in Dynamic Memories," IEEE Transactions on Electronic Devices, vol. 26, Issue1, pp: 2-9, January 1979.
http://dx.doi.org/10.1109/T-ED.1979.19370

[3] J. F. Ziegler and W. A. Lanford, "The effect of Cosmic Rays on Computer Memories," Science, vol. 206, No. 776, 1979.

[4] S. Mitra, N. Seifert, et,al, "Robust system design with built-in soft-error resilience," IEEE Computer, 2005, 38(2): 43-52.

[5] Karlsson, J., Liden, P., Dahlgren, P., Johansson, R., Gunneflo, U., "Using heavy-ion radiation to validate fault-handling mechanisms," Micro, IEEE Volume 14, Issue 1, Feb. 1994 Page(s):8 - 23

[6] Sosnowski,J., "Transient fault tolerance in digital systems," Micro, IEEE, Volume 14, Issue 1, Feb. 1994 Page(s):24 - 35

[7] D. C. Bossen, A. Kitamorn, K. F. Peick, and M. S. Floyd, "Fault-Tolerant Design of the IBM pSeries 690 Using POWER4 Processor Technology," IBM Journal of Research and Development, vol. 46, No. 1, pp:77-96, 2002.
http://dx.doi.org/10.1147/rd.461.0077

[8] A. Wood. Data integrity Concepts, "Features and Technology," White paper, Tandem Division, Compaq Computer Corporation.

[9] W. W. Peterson and E. J, Weldon. Error-Correcting Codes, MIT Press, 1961.

[10] A Mendelson and N Suri, "Designing high-performance & reliable superscalar architectures: The out of order reliable superscalar (O3RS) approach," In: Proc of IEEE/IFIP Int’l Conf on Dependable Systems and Networks, New York, 2000, 473-481

[11] D. M. Tullsen, S. J. Eggers and H. M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism". In: Proc. of 22nd Annual International Symposium on Computer Architecture, Santa Marguerite Liguria, Italy, 1995, pp: 392-403.
http://dx.doi.org/10.1109/ISCA.1995.524578

[12] D. T. Marr, F. Binns, D. L. Hill, G. Hinton, D. A. Koufaty, J. A. Miller, and M. Upton. Hyper-Threading Technology Architecture and Microarchitecture [J]. Intel Technology Journal, Vol. 6, No. 1. February 2002, pp: 4-15.

[13] R. P. Preston et al, "Design of an 8-Wide Superscalar RISC Microprocessor with Simultaneous Multithreading," In: Proc. Of IEEE International Solid-State Circuits Conference, San Francisco, USA, February 2002, pp: 334–335.

[14] Eric Rotenberg, "AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors," In: Proc. Of 29th International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, 15-18 June, 1999, pp: 84-91.

[15] S. K. Reinhardt and S. S. Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," In: Proc. Of the 27th International Symposium on Computer Architecture, Vancouver, British Columbia, Canada, 10-14 June, 2000, pp: 25-36.

[16] T.N. Vijaykumar, Irith Pomeranz and Karl Cheng, "Transient-Fault Recovery Using Simultaneous Multithreading," In: Proc. Of the 29th Annual International Symposium on Computer Architecture, Anchorage, Alaska, 25-29 May, 2002, pp: 87-98.

[17] A. Sodani and G. S. Sohi, "Dynamic Instruction Reuse," In: Proceedings of 24th Annual International Symposium on Computer Architecture (ISCA), Denver, Colorado, USA, June 1997, pp: 194-205.
http://dx.doi.org/10.1145/264107.264200

[18] A. Parashar, S. Gurumurthi, and A. Sivasubramaniam, "A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy,”In: 31st Annual International Symposium on Computer Architecture (ISCA), pp. 376–386, June 2004.
http://dx.doi.org/10.1109/ISCA.2004.1310789

[19] M. A. Gomaa and T. N. Vijaykumar, “Opportunistic Fault Detection,” In: 32nd Annual International Symposium on Computer Architecture (ISCA), pp. 172–183, Madison, Wisconsin, USA, June 2005

[20] A. Parashar, S. Gurumurthi, and A. Sivasubramaniam, “SlicK: Slice-Based Locality Exploitation for Efficient Redundant Multithreading,” In: 12th Annual International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 95–105, October 2006
http://dx.doi.org/10.1145/1168857.1168870

[21] Dean M. Tullsen and Jeffery A. Brown, "Handling Long-latency Loads in a Simultaneous Multithreading Processor," In: Proc. Of the 34th IEEE International Symposium on Microarchitecture, Austin, USA, 1-5 Dec 2001, pp: 318-327.

[22] J. Sharkey, "M-Sim: A Flexible, Multi-threaded SimulationEnvironment," Tech. Report CS-TR-05-DP1, Department of Computer Science, SUNY Binghamton, 2005.

[23] Seungryul Choi and Donald Yeung, "Learning-Based SMT Processor Resource Distributing via Hill-Climbing," In: Proc. of the 33rd International Symposium on Computer Architecture, Boston, MA, USA, 17-21 June, pp: 239-251.

[24] T. Sherwood, et al, "Automatically Characterizing Large Scale Program Behaviour," In: Proc. of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, 5-9 October, pp: 47-57.

[25] Steven E. Raasch and Steven K. Reinhardt, "The impact of resource partitioning on SMT processors, " In: Proc of the 12th International Conference on Parallel Architecture and Compilation Techniques, New Orleans, Louisiana, 2003, pp: 15-25.

[26] Francisco J. Cazorla, Alex Ramirez, Mateo Valero et al, "Dynamically controlled resource allocation in SMT processors, " In: Proc of the 37th International Symposium on Microarchitecture, Portland, 2004, pp: 171-182.

[27] Hua Yang, Gang Cui and Xiaozong Yang, "Eliminating inter-thread interference in register file for SMT processors,". In: Proc of the 6th International Conference on Parallel and Distributed Computing, Applications and Technologies, Dalian, 2005, pp: 40-45.