Extraction and Simulation of Intra-gate Defects Affecting CMOS Libraries

Abstract

Shorts and opens are the most common type of defects in digital integrated circuits ICs. They can affect interconnect wires connecting gates or transistors inside. Tools targeting the extraction of these potential defects focus only on the inter-gate bridging faults, and no one presents a solution to extract potential intra-grate bridging faults, open and resistive-open defects. This paper presents an automated approach to extract and simulate potential intragate defects in standard cell library, based on the use of verification and simulation CAD tools. As application, we used these fault signatures to diagnose different types of intra-gate defects. Experimental results show the efficiency of our approach to isolate injected defects on industrial designs.