Implementation of Low Density Parity Check Decoders using a New High Level Design Methodology

Abstract

Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However hardware implementation of LDPC decoders using traditional hardware description language (HDL) based approach is a complex and time consuming task. This paper presents an efficient high level approach to designing LDPC decoders using a collection of high level modelling tools. The proposed new methodology supports programmable logic design starting from high level modelling all the way up to FPGA implementation. The methodology has been used to design and implement representative LDPC decoders. A comprehensive testing strategy has been developed to test the designed decoders at various levels. The simulation and implementation results presented in this paper prove the validity and productivity of the new high level design approach.