Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

Abstract

The complexity in timing optimization of high performance microprocessors has been increasing with the number of channel-connected transistors in various paths of dynamic CMOS circuits and the rising magnitude of process variations in nanometer CMOS process. In this paper, a process variation aware transistor sizing algorithm for dynamic CMOS circuits while considering the Load Balance of Multiple Paths (LBMP) is proposed. The proposed iterative optimization algorithm is a deterministic approach and is illustrated first by a 2-b weighted binary-to-thermometric converter (WBTC) and of which the critical path was optimized from an initial delay of 355 ps to an optimal delay of 157 ps, which accounts for a 55.77% delay improvement. A 4-b unity weight binary-to-thermometric converter (UWBTC) was also designed and of which the critical path was optimized from an initial delay of 152 ps to an optimal delay of 103 ps, which accounts for a 32.23% delay improvement. Finally, a 64-b parallel binary adder was partitioned to a mixed dynamic-static CMOS style and the critical path and the power delay product were optimized to 632 ps and 84.17 pJ respectively.