Compiler Back End Design for Translating Multi-radio Descriptions to Operating System-less Asynchronous Processor Datapaths

Abstract

Most asynchronous processor Instruction Set Architectures (ISA) are based on a single type of underlying asynchronous circuit design style. Asynchronous processor ISAs are entirely dependent on the type of asynchronous design style chosen and can support a limited set of simple applications only. Design reuse is typically difficult to realize in such cases. In this paper, we show a behavioral model of a predictor circuit system that configures an application profile-driven asynchronous processor ISA comprising two asynchronous design styles. The predictor circuit system is used to translate application profile and multi-radio code to the processor datapath through a compiler back-end. The target is an asynchronous processor that does not run an operating system and is used both as a complement and alternate to software-defined radios with high degrees of design reuse.